102+ Applicants
Posted: 8 months ago
5-12 years
Karnataka
Work from Office
Posted: 8 months ago
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Applicants: 103+
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Job Description
- As a Senior Analog Circuit Design Engineer for High-Speed Interface - PLL at Samsung Semiconductor India R&D Center in Bangalore, you will have the opportunity to work on cutting-edge silicon solutions that push the limits of computing. With 5-12 years of relevant experience in Analog and Mixed Signal Design, you will be responsible for designing low jitter and high-frequency PLLs, both LC and Ring-based, as well as General Purpose ADCs, thermal sensors IP, high-speed Serdes, LDOs, BGRs, and other power management blocks. Your role will involve full IP design cycle exposure in advanced Samsung foundry processes of 4nm and below.
You will be part of a team that thrives on solving complex digital design challenges and is passionate about creating high-performance hardware architectures. Your expertise in computer architecture and storage systems will be highly valued as you contribute to the development of innovative semiconductor solutions that cater to a wide range of market segments, from hyper-scale data centers and automotive to IoT, mobile, and consumer electronics.
Working at Samsung Semiconductor India R&D Center, the largest R&D center outside Korea for Samsung Electronics, you will collaborate with engineers involved in strategic projects and cutting-edge technologies. Your role will offer diverse exposure to different domains, projects, products, clients, and countries, allowing you to conduct research in new and emerging areas of technology. Innovation and creativity are key values at SSIR, and you will play a crucial role in providing high reliability, high performance, and value-added services that contribute to Samsung Electronics" excellence in product delivery.
If you are ready for a challenging design experience and keen on silicon validation, we invite you to share your CV with us at
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Skills
Storage SystemsHigh Speed InterfaceHigh Frequency PLL DesignIP Design CycleLC PLL DesignThermal Sensors IP DesignBGR DesignSilicon ValidationMixed Signal DesignComputer ArchitecturePLLAnalog Circuit DesignHigh Speed Serdes DesignPower Management Blocks DesignLow Jitter PLL DesignLDO DesignRing Based PLL DesignSamsung Foundry ProcessAnalogGeneral Purpose ADC DesignIf an employer asks you to pay any kind of fee, please notify us immediately. Jobaaj does not charge any fee from the applicants and we do not allow other companies also to do so.
Important dates & deadlines?
Application Deadline
19 Oct 25, 12:06 PM IST
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