Sr Staff Engineer, Physical Design - AI/ML Accelerator IP Development

About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFives unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on peoples lives; making the world a better place, one processor at a time.
Are you ready
To learn more about SiFives phenomenal success and to see why we have won the GSAs prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
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At SiFive, were building cutting-edge RISC-V based processors and accelerator IP for the next wave of high-performance computing. As part of our Physical Design team, youll own pushing Power, Performance, and Area (PPA) boundaries for our AI/ML accelerator IP. Join us in a fast-paced, collaborative environment where continuous learning, ownership, and impact are part of everyday work.
Responsibilities - What Youll Do

• Own the implementation of AI/ML accelerator IP from RTL to GDS, deliver best-in-class PPA at block and subsystem levels.

• Collaborate with design and architecture teams to optimise design/architecture for implementation, including path-finding for the next generation of AI/ML accelerator IP development.
• Contribute to physical design methodologies, flows, automation, technology/IP evaluations etc.
  

Requirements - What Youll Bring

• 8+ years of physical design experience with PPA critical IPs.
• Proven ability to optimize for aggressive PPA targets using advanced physical design techniques.
• Strong technical problem-solving skills, detail-oriented mindset and clear communication.
• Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence implementation tools.
• Bachelors or Masters in Electrical or Computer Engineering.
  

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Why join us

• Be part of the RISC-V movement and help define the future of computing architecture.
• Work on high-impact IP that powers real-world AI and ML workloads.
• Collaborate with world-class engineers in a supportive, fast-paced, learning environment.
• Enjoy a culture that values innovation, ownership, and technical excellence.
  

Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.