Rtl Designer

Were Hiring – RTL Design / Low-Power Verification Engineer (UPF / VCLP Expert)

Are you passionate about RTL Design and Low-Power SoC Verification?

Join ACL Digital and be part of an innovative semiconductor design team driving next-gen chip solutions!

Location: Bangalore
Experience: 5+ Years
Notice Period: Immediate to 30 Days

What You’ll Do

• Define, develop, and validate Unified Power Format (UPF) for multi-voltage, power-gated SoC/ASIC designs.
  
• Perform
  
  power intent verification using Synopsys VC LP / PrimeTime PX / Cadence CLP.
  
• Analyze and close VCLP warnings and errors — isolation, retention, and level shifter strategies.
  
• Collaborate with RTL & PD teams to ensure correct low-power cell integration.
  
• Support dynamic low-power simulation (VCS LP / Xcelium LP).
  
• Drive power-aware STA and power-up/power-down sequencing validation.
  
• Contribute to power signoff before tape-out.
  

What We’re Looking For

• Hands-on experience with RTL Design, UPF, and Low-Power SoC Methodologies.
  
• Proficiency in Verilog/SystemVerilog, TCL/Python/Perl scripting.
  
• Familiarity with Synopsys or Cadence low-power toolchains.
  
• Strong understanding of isolation, retention, and level-shifter techniques.
  
• Excellent debugging, analytical, and communication skills.
  

Be part of a team that designs tomorrow’s semiconductors, today!

Apply Now: prabhu.p@acldigital.com
WhatsApp: +91 87543 87484