Strategic / Leadership - Verification

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, youll discover the real differentiator is our culture. We push the limits of innovation to solve the worlds most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
Fellow – Verification Architect
Location: [Insert Location]
Job Category: Engineering – Technical Leadership
Career Track: Fellow (Technical Ladder)
Reports To: [Insert Hiring Manager]
The Role
At AMD, we push the boundaries of innovation. As a Fellow-level Verification Architect, you will define and lead the verification architecture and methodology for next-generation high-speed interface PHY IP designs (DDR, LPDDR, USB, PCIe, and emerging standards). You will set the strategic direction for complex UVM testbench architectures, drive methodology innovation (including HW/SW co-verification and

AI-assisted flows), and ensure scalable, high-quality verification outcomes across global programs.
Key Responsibilities

• Architect & Own Verification Strategy: Define end-to-end verification architecture for interface PHY IP and subsystems, aligning test strategies, metrics, and sign-off criteria.
• Advanced Testbench Leadership: Develop modular, reusable UVM-based environments; standardize VIP/UVC/BFM usage; enable scalable stimulus, checkers, monitors, and scoreboards.
• HW/SW Co‑Verification:
• Establish flows that integrate firmware/driver components with RTL to validate initialization, calibration, training sequences (e.g., DDR write‑leveling/read‑gate, PCIe link training, USB enumeration).
• Deploy virtual platforms/emulation (e.g., FPGA/proto, hybrid, co-simulation) for early SW bring-up, performance, and corner-case coverage.
• Define interfaces for pre‑silicon validation of boot flows, power management, and field-update scenarios.
• AI‑Driven Verification Improvements:
• Introduce ML/AI techniques for seed selection, test generation, coverage hole prediction, and regression triage.
• Apply anomaly detection and clustering to log/FSDB analytics, accelerating debug and root-cause localization.
• Champion data pipelines/telemetry to continuously improve coverage closure and failure reproduction.
• Methodology & Tools Innovation: Evolve coverage models (functional/code/toggle), integrate formal, static (CDC/RDC/Lint), power-aware (UPF) checks, and drive automation in build/run/report pipelines.
• Cross‑Functional & Global Leadership:
• Lead distributed teams across sites/time zones; harmonize processes, reviews, and sign-off standards.
• Partner with design/architecture/validation to align requirements, assumptions, and corner cases; facilitate spec clarity and executable verification plans.
• Quality, Metrics & Sign-off: Define quantitative KPIs (e.g., coverage targets, escape rates, bug‑find efficiency), and enforce rigorous tape‑out criteria for PHY IPs and subsystems.
• External Representation: Publish/present in industry forums, contribute to standards, and reinforce AMDs leadership in verification technology.
  

Preferred Qualifications

• 20+ years in ASIC/IP verification with deep expertise in high‑speed interface PHYs (DDR/LPDDR, USB, PCIe; CXL/DisplayPort is a plus).
• Mastery of SystemVerilog/UVM, constrained‑random, assertion‑based verification, coverage modeling, and scoreboard/reference-model design.
• Proven experience architecting HW/SW co‑verification flows: driver/firmware integration, protocol training sequences, pre‑silicon boot/power flows, and emulation/prototyping.
• Demonstrated impact using AI/ML in verification (test generation, coverage guidance, log triage, flaky test detection, failure clustering).
• Strong background in formal verification, CDC/RDC/Lint, power‑aware (UPF), and DFX sign‑off.
• Track record of methodology creation/adoption across multiple programs; hands-on leadership in global, cross‑site teams.
• Patents/publications and recognized contributions in verification methodology or interface technologies.
  

Leadership Expectations at Fellow Level

• Technical Expertise: Be AMDs recognized Fellow of Verification Architecture—set the bar for IP/subsystem verification excellence.
• Innovation: Create and scale breakthrough methodologies (HW/SW convergence, AI‑assisted flows) that materially improve quality and schedule.
• Impact: Deliver strategic outcomes measured by coverage attainment, escape minimization, regression efficiency, and successful tape‑outs across product lines.
  

Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMDs Responsible AI Policy is available here.
This posting is for an existing vacancy.