Design Verification Engineer

Experience and Qualification

Bachelors/Masters degree in engineering in Electronics and Electrical Engineering with excellent academic records.

• 3 - 5 years of experience in Functional Verification
• Exposure to DV of High Speed Interface IPs/SerDes/Analog Mixed Signal IP(PHY, PLLs, ADC/DAC, Sensors etc) is preferred.
• Knowledge in one of the interfaces like USB, PCIe, Ethernet, HDMI, MIPI is a plus.
• High Proficiency in Verification Methodologies (UVM/OVM), SV and Verilog.
• Should have very good experience in deep RTL/Design debugging and Bug Hunting.
• Expert in building Reusable, Scalable Verification Environment from scratch with very good understanding of each building blocks and coding guidelines.
• Exposure to Gate Level Simulations and Formal Verification is desirable.
• 
  Expertise in verification planning and effort estimation.
• Exposure to Analog and Digital behavioral modelling will be a plus.
• Good understanding of Test bench architecture.
• Working knowledge of Scripting in Perl/Python/Shell.
• Proficiency in industry-standard EDA tools for Simulation.
• Exposure to signal performance parameters like noise and jitter.
• Excellent problem-solving, analytical, and communication skills.
• Ability to work effectively in a collaborative team environment.
• Understanding of MATLAB and/or Python libraries such as NumPy would be an added advantage.

Role: As a Digital Verification- (DMS) , you will play a crucial role in verification sign off of High Performance Analog Mixed Signal products. The successful candidate in this role will be part of team defining efficient verification methodologies and designing state of art testbenches related to mixed-signal designs. We are seeking individuals who have a strong verification base, are open to work on mixed signal designs and are extremely passionate about verification, quality and thrive in solving complex challenges. The key expectations for this role include, but are not limited to:

• Thorough understanding of detailed Verification Flow.
• Drive verification closure using Metrics Driven Approach.
• Should develop good understanding of design and be able to provide pointers during failure debugs.
• Should be able to create reusable efficient verification testbenches from scratch.
• Experience with 3rd Party VIPs is a plus.
• Should have ability to effectively work with cross domain teams for better DV quality and quick issue closure
• Effectively employ scripting to improve productivity.
• Drive innovation by exploring new techniques and emerging technologies.
• Collaborate with customers and partners to understand their requirements and provide customized solutions.
• Provide technical guidance and mentorship to junior members of the team.