Verification Engineer (Verilog, System Verilog, C/C Based Verification, UVM) - ONSITE JOB - INDEPENDENT CONSULTANTS ONLY - C2H

Location : 100% onsite in either Austin TX OR Sunnyvale, CA
Length: 6-month Contract-to-Hire :
Visa - There are no visa restrictions (H1s need a copy of I-797 showing MethodHub Software as the petitioner
Need to be local to either Austin or Sunnyvale, the final interview is onsite.

• 7 + years experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle
• Experience in the development of UVM based verification environments from scratch
• Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs

Minimum Qualifications

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• B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
• Hands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodology
• Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.

Preferred Qualifications

• Experience with revision control systems like Mercurial(Hg), Git or SVN