Senior DFT Engineer

Company Description Emarlex Multiventure is an IT Services, HR Consulting, and Business Solutions company that helps organizations accelerate growth through technology, talent, and digital transformation. The company partners with startups, SMEs, and enterprises to deliver end-to-end workforce and business solutions that support high-performing teams and streamlined HR operations. Its expertise spans IT and non-IT recruitment, HR consulting, staffing solutions, HRMS implementation, payroll services, and digital business consulting. As an implementation and consulting partner, Emarlex Multiventure focuses on improving operational efficiency, employee experience, and compliance through cloud-based HRMS and modern business applications. With a customer-first approach, the company delivers scalable solutions that help businesses hire smarter, operate efficiently, and grow with confidence.

Role Description The Senior Design For Test (DFT) Engineer role at Emarlex Multiventure is a full-time, on-site position based in Bengaluru South. This role involves defining and implementing DFT architectures, including scan, MBIST, boundary scan, and other testability features for complex SoCs and ASICs. The Senior DFT Engineer will develop test plans, create and validate test patterns, work with RTL and physical design teams to integrate DFT structures, and perform debug and coverage analysis. The role includes close collaboration with product engineering, verification, and manufacturing test teams to ensure robust test strategies, optimized test time, and high-quality silicon. The engineer will also mentor junior team members, contribute to methodology improvements, and support customer requirements and design reviews.

Qualifications

• Candidates should possess strong DFT skills such as scan insertion, ATPG, MBIST, boundary scan, and test coverage analysis.
• Candidates should possess solid digital design and verification skills, including RTL (Verilog/SystemVerilog), simulation, and understanding of synthesis and timing concepts.
• Candidates should possess experience with EDA tools for DFT and physical design flows (e.g., Synopsys, Cadence, or Mentor tools relevant to scan, BIST, and test implementation).
• Candidates should possess semiconductor product and test knowledge, including SoC/ASIC development flows, ATE test program development, and silicon debug.
• Candidates should possess strong analytical, problem-solving, and documentation skills, with the ability to collaborate across cross-functional engineering teams.
• Bachelors or Masters degree in Electronics, Electrical Engineering, Computer Engineering, or a related field, with several years of relevant DFT experience in VLSI/semiconductor industry.
• Experience in leading DFT projects, mentoring engineers, and driving methodology improvements will be highly beneficial.