Staff Engineer Formal(IOMMU-N)

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

:

Responsibilities:

• Develop and implement formal verification plans for complex digital designs, primarily targeting RISC-V processors and other IP blocks designed in Chisel.
• Write and debug formal properties (assertions and assumptions) in Chisel/Scala to specify design behavior and identify corner-case bugs.
• Utilize formal verification tools to prove design correctness and uncover potential issues.
• Collaborate closely with design engineers to understand design specifications, review architectures, and provide formal verification feedback.
• Develop verification environments and infrastructure using Chisel, Scala, and TCL scripting.
• Identify and implement strategies for improving formal verification efficiency and coverage, including functional coverage and constrained-random verification techniques seen in methodologies like UVM adapted for Chisel.
• Analyze formal verification results, debug failures, and work with the design team to resolve issues.
• Contribute to the continuous improvement of our formal verification flows and methodologies.​

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of hands-on experience in formal verification of digital hardware designs.
• Proficiency in Scala programming, with hands-on experience in Chisel hardware description language.
• Strong understanding of formal verification methodologies (e.g., assertion-based verification, model checking, equivalence checking).
• Experience in writing effective formal properties and assertions. Tools like chisel-formal use Formal traits and assert statements within Chisel modules for this purpose github.com.
• Familiarity with formal verification tools and their application
• Experience with TCL scripting for tool automation and flow development.
• Solid understanding of digital design principles, computer architecture, and FPGA/ASIC design flows.
• Excellent problem-solving skills and a keen eye for detail.
• Strong communication and collaboration abilities.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.