Formal Verification

KEY RESPONSIBILITIES

• Develop, run, and maintain Connectivity and RAS formal regressions.
• Execute Connectivity, SEQ, XPROP, and selected Clock Gating Verification activities.
• Debug failing checks, analyze waveforms, identify root causes, and drive issues to closure.
• Track coverage, convergence, and signoff readiness for assigned areas.
• Leverage AI tools and automation to accelerate verification execution, debugging, and analysis.

REQUIRED EXPERIENCE

• 3–6 years of ASIC/SoC verification experience with exposure to formal verification.
• Hands-on expertise in Connectivity Verification, SEQ, and/or XPROP. FPV is a plus.
• Strong debugging and root-cause analysis skills.
• Understanding of formal verification fundamentals, coverage, and convergence concepts.
• Experience using AI-assisted workflows to improve engineering productivity is highly desirable.

PERSONAL ATTRIBUTES

• Strong attention to detail and execution rigor.
• Self-driven, accountable, and sincere.
• Go-getter attitude with a bias for action.
• Effective and practical user of AI tools; ability to leverage AI to deliver faster, higher-quality results is a must.

EDUCATION

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.