ASIC Physical Design, Senior Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of physical design, taking complex IP from RTL to GDS, and you know that the difference between a design that tapes out on schedule and one that slips is usually a decision you made during floorplanning or a timing path you caught in week two instead of week ten. You have seen enough 5nm and below tapeouts to know where the landmines are buried, and you are the engineer who spots them before they blow up the schedule.

You do not wait for perfect specs. When the RTL is still settling and the foundry deck has a known issue, you start floorplanning anyway because you know what matters and what can wait. You have strong opinions about ICC2 strategies, about when to push timing versus area, about which corners actually matter for signoff. You are comfortable defending those opinions in a room full of architects and verification leads, and you are equally comfortable changing your mind when the data says you should.

At Synopsys, you will be working on UCIe PHYs and testchips that define how chips connect in the next generation of systems. The designs are real, the nodes are leading edge, and the team expects you to lead, not just execute.

What You'll Be Doing

• Own physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and more advanced nodes
• Drive synthesis, place and route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV across multiple concurrent projects
• Work directly with verification, DFT, and IP integration teams to resolve design issues, close timing, and meet PPA targets without slipping the schedule
• Lead design reviews, present tradeoff analyses, and make real-time decisions on floorplan changes, clock tree strategies, and signoff waivers
• Pilot new physical design flows and advanced node methodologies, then document what worked and what did not for the rest of the team
• Mentor junior engineers on timing closure techniques, physical verification strategies, and how to navigate the ICC2 toolchain effectively
• Interface with foundry partners and customer engineering teams to resolve technology file issues, DRC/LVS challenges, and silicon bring-up questions

The Impact You Will Have

• Deliver production-quality UCIe PHY designs that enable next-generation chip-to-chip connectivity for Synopsys customers building AI accelerators, data center processors, and high-performance compute systems
• Improve design cycle time and PPA outcomes by driving tooling and methodology improvements across the physical design flow that the entire IP team will adopt
• Handle multiple concurrent tapeouts in leading-edge technologies, ensuring Synopsys meets customer commitments and maintains its reputation for on-time silicon delivery
• Strengthen customer confidence in Synopsys IP through high-quality signoff, responsive technical engagement during integration, and designs that actually work in silicon
• Influence product roadmap decisions by surfacing design insights and PPA tradeoffs that matter to end customers during architecture and planning phases
• Contribute to how Synopsys approaches physical design for 3nm and beyond by piloting new flows, feeding lessons learned back into the methodology team, and shaping best practices
• Enable faster time-to-market for customers by delivering UCIe IP that integrates cleanly, meets timing out of the box, and requires minimal rework during SoC integration

What You'll Need

• 5-15 years of hands-on experience in ASIC physical design, with demonstrated expertise in synthesis, place and route, timing closure, and physical verification
• Multiple tapeouts and signoffs in 5nm or more advanced process nodes, you have taken designs all the way to GDS and dealt with the messiness that comes with it
• Proficiency with industry-standard tools including DC, PT, ICC2/FC, and ICV, you know the commands, the flow, and the workarounds
• Proven track record working on SoC or IP tapeouts where you owned significant portions of the physical design and were accountable for signoff
• Strong understanding of FinFET technology and the physical design challenges specific to advanced nodes, including multi-patterning, electromigration, and IR drop at scale
• Experience with DFT insertion, scan chain routing, and ATPG is a strong plus, especially if you have debugged DFT-related timing or physical issues
• Exposure to UCIe, SerDes, or high-speed interface IP is valuable but not required, we care more about your physical design depth and ability to learn quickly

Who You Are

• You can walk into a timing review with 500 failing paths and know within ten minutes which ones actually matter and which ones are tool artifacts or false paths
• You are comfortable making tradeoff calls under pressure, like choosing to upsize a cell and take the area hit because you know the timing margin is real and the schedule cannot slip
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