Sr Staff High-Speed Interface Verification Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of mixed-signal verification, and you know that the hardest problems live at the boundary where digital meets analog. You are the engineer who can read a waveform, spot the timing violation that three others missed, and trace it back to a testbench assumption made two months ago. You do not just run regressions, you architect verification strategies that catch the subtle, the corner case, the thing that only shows up at 56 Gbps under specific PVT conditions.

What You'll Be Doing

• Lead verification of high-speed SerDes IP using UVM and SystemVerilog testbenches in mixed-signal co-simulation environments
• Define, track, and execute verification test plans for PCIE, Ethernet, USB3.1, and other high-speed protocols from architecture through tapeout
• Debug simulation failures across digital and analog domains, working directly with waveform viewers, mixed-signal simulators, and protocol analyzers
• Build and extend UVM testbenches with constrained random sequences, coverage models, and checkers that target real-world corner cases
• Collaborate daily with digital, analog, and mixed-signal design teams to align verification strategy with design intent and silicon bring-up realities
• Manage customer escalations by reproducing issues, root-causing failures, and driving resolution with engineering and field teams
• Drive pre-sales and post-sales technical discussions with customers, translating verification results into confidence and clarity

The Impact You Will Have

• Ensure that SerDes IP shipping to customers meets performance, functionality, and reliability targets before it ever reaches silicon
• Reduce post-silicon debug cycles by catching mixed-signal integration issues early through rigorous co-simulation and coverage-driven verification
• Set the technical direction for verification methodology across current and next-generation SerDes products
• Accelerate customer adoption and satisfaction by resolving escalations quickly and providing clear, actionable technical guidance
• Mentor and elevate the verification team by establishing best practices, code reviews, and a culture of ownership and quality
• Contribute directly to Synopsys IP competitiveness by delivering verification environments that scale across protocol variants and process nodes
• Influence product roadmaps by surfacing verification insights that shape architecture and design decisions upstream

What You'll Need

• MTech or BTech in Electronics, Electrical Engineering, Computer Science, or equivalent with 7+ years of hands-on verification experience in ASIC or mixed-signal environments
• Deep expertise in UVM, SystemVerilog, and verification methodologies including constrained random testing, functional coverage, and assertions
• Proven experience with digital/analog co-simulation tools and methodologies, including AMS simulators and mixed-signal verification flows
• Working knowledge of high-speed interface protocols such as PCIE, Ethernet, or USB3.1, including protocol-level verification and compliance
• Strong understanding of the full ASIC development flow from architecture specification through RTL design, verification, and hardware bring-up
• Experience writing complex system-level testbenches in UVM, including sequence libraries, scoreboards, and protocol monitors
• Hands-on experience debugging waveform-level failures in both digital logic and analog circuit behavior

Who You Are

ul style='--tw-border-spacing-x: 0; --tw-border-spacing-y: 0; --tw-translate-x: 0; --tw-translate-y: 0; --tw-rotate: 0; --tw-skew-x: 0; --tw-skew-y: 0; --tw-scale-x: 1; --tw-scale-y: 1; --tw-pan-x: ; --tw-pan-y: ; --tw-pinch-zoom: ; --tw-scroll-snap-strictness: proximity; --tw-gradient-from-position: ; --tw-gradient-via-position: ; --tw-gradient-to-position: ; --tw-ordinal: ; --tw-slashed-zero: ; --tw-numeric-figure: ; --tw-numeric-spacing: ; --tw-numeric-fraction: ; --tw-ring-inset: ; --tw-ring-offset-width: 0px; --tw-ring-offset-color: #fff; --tw-ring-color: rgb(59 130 246/0.5); --tw-ring-offset-shadow: 0 0 #0000; --tw-ring-shadow: 0 0 #0000; --tw-shadow: 0 0 #0000; --tw-shadow-colored: 0 0 #0000; --tw-blur: ; --tw-brightness: ; --tw-contrast: ; --tw-grayscale: ; --tw-hue-rotate: ; --tw-invert: ; --tw-saturate: ; --tw-sepia: ; --tw-drop-shadow: ; --tw-backdrop-blur: ; --tw-backdrop-brightness: ; --tw-backdrop-contrast: ; --tw-backdrop-grayscale: ; --tw-backdrop-hue-rotate: ; --tw-backdrop-invert: ; --tw-backdrop-opacity: ; --tw-backdrop-saturate: ; --tw-backdrop-sepia: ; --tw-contain-size: ; --tw-contain-layout: ; --tw-contain-paint: ; --tw-contain-style: ; box-sizing: border-box; border: 0px solid rgb(229, 231, 235); list-style-position: initial; list-style-image: initi