Staff Engineer, SRAM Memory

Staff Memory Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the analog and mixed-signal trenches, designing memory circuits that have to work across voltage corners, temperature extremes, and process variations without a second chance. You know that an SRAM bitcell is not just six transistors on a page, it is a tradeoff between read stability, write margin, leakage, and area, and you have made those calls enough times to know which knob to turn when a design is not closing.

You think in terms of transistor-level behavior, not just simulation results. When a memory fails at a corner, you do not just re-run SPICE, you go back to the schematic, check your layout parasitics, and figure out what actually broke. You have worked closely with layout teams, and you understand that a good floorplan saves you three weeks of iteration later.

You are comfortable owning a memory block from architecture through tapeout. You can sit with a compiler team and explain why your bitcell needs a specific routing constraint, then turn around and review a layout with a physical design engineer without losing context. At Synopsys, you will design embedded memories that ship in our IP portfolio and power chips across the industry.

What You'll Be Doing

• Design and develop embedded CMOS memories including single-port SRAM, dual-port SRAM, register files, and ROM for Synopsys IP products
• Own circuit architecture and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurations
• Perform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verification
• Develop and verify bitcells, define layout rules, and drive layout design and parasitic extraction closure with the physical design team
• Interface with CAD teams to integrate memory designs into compiler automation flows and generate EDA models for customer use
• Collaborate with frontend engineers to define and validate full verification flows including timing, power, and functional models
• Mentor junior engineers and lead technical aspects of memory design projects from concept to delivery

The Impact You Will Have

• Your memory designs will ship as part of Synopsys IP offerings used by semiconductor companies worldwide in high-volume production chips
• The bitcells and architectures you develop will define performance, power, and area benchmarks for next-generation embedded memory IP
• Your layout planning and verification rigor will reduce tapeout risk and speed time to market for memory compiler releases
• The automation flows you help define will enable faster, more reliable memory generation for customers across process nodes
• Your technical mentorship will build design capability within the team and raise the quality bar for future memory products
• The tradeoffs you make between speed, power, and density will directly influence customer adoption and competitiveness in the IP market
• Your collaboration with CAD and frontend teams will improve tooling, models, and verification coverage across the memory IP portfolio

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related technical field
• Deep hands-on experience with CMOS memory circuit design including SRAM, register files, or ROM
• Proficiency with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based simulators
• Strong understanding of memory layout design, parasitic extraction, and layout verification tools like Calibre or Assura
• Scripting capability in C-Shell, Perl, or similar languages; experience with C++ or JavaScript is a plus
• Demonstrated ability to lead technical projects and mentor junior engineers through complex design challenges
• Experience working with memory compiler flows, EDA model generation, or design automation is a strong plus

Who You Are

• You can look at a bitcell schematic and immediately spot a read stability issue or a leakage path without running a full simulation
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