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Job Description
-Chip design flow, from RTL to GDSII, ensuring design efficiency.
-EDA tools (Synopsys, Cadence, Siemens EDA)
-Timing optimization and STA
-Maintain scripts in Python and Tcl
Required Candidate profile
-5+ years of experience in chip design-Proficiency in HDLs (Verilog, SystemVerilog)
-Strong scripting skills in Python and Tcl.
-Hands-on experience with Synopsys, Cadence, or Siemens EDA tools.
Perks and benefits
Position: Electronic Design Automation EngineerSkills
Chip DesignAutomation EngineeringElectronics Hardware DesignSTAUpfLow Power DesignHardware DesignFunctional SafetyIf a job posting appears fraudulent, asks for payment, contains misleading information, or violates our guidelines, please report it immediately. Our team will review it promptly, Jobaaj does not charge any fee from the applicants.
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