Engineer II - CAD

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our we affectionately refer to it as the and its won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

Visit our page to see what exciting opportunities and company await!

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• The CAD group at Microchip offers global support for technologies and tools used in product development providing innovative solutions for the design community.
• A successful candidate in this role will participate in various aspects of EDA support and developing next-generation ASIC design flow and methodology.
• He / She will also work closely with various business units across the globe to understand their needs and foster innovative ideas to solve complex problems.

Key Requirement :

• Good Knowledge of design flows from RTL design through synthesis, formal verification, and timing closure for RTL2GDS delivery.

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• Design, benchmark, and deploy automated CAD tool flows focusing on logic synthesis, hierarchical optimization, physical synthesis, and chip sign-off timing.
• Automation & Tools Customization: Write and optimize highly robust, scalable scripts using Tcl and Python to reduce Flow Turnaround Time (TAT) and build automated tracking tools for timing data.
• Synthesis & Equivalence Verification: Build and optimize front-end flows utilizing advanced tools for logical/physical synthesis and Formal Verification/Logic Equivalence Checking (LEC).
• Hands-on experience with one or more of the following industry-standard toolsets: Synopsys Fusion Compiler, DC, PrimeTime Cadence Genus, Tempus or Innovus
• Exposure to leveraging AI driven EDA capabilities (e.g., Synopsys FC.ai, Cadence Cerebrus) to automate PPA exploration and timing closure optimization.
• Standardize and automate the validation of Synopsys Design Constraints (SDC) across all functional and test modes.
• Partner directly with major EDA vendors to test next-generation features, troubleshoot internal tool failures, and adapt flows for deep sub-micron advanced process nodes.
• Excellent verbal and written communication skills.

Requirements/Qualifications:

• B.E./B.TECH/M.E./M TECH (Electronics/ECE/CS/VLSI).
• 2 to 8 Years of relevant experience is required