Verification Lead

Lead Verification engineer

Responsibilities

As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices.

Requirements

• Bachelors/ Masters degree or higher in EEE/ECE
• 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification.
• Experience using multiple verification platforms: UVM test bench, emulator, software environments
• Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc.
• Experience defining verification methodologies
• Experience with test plan development, test bench infrastructure, developing tests and verifying the design
• Experience with writing directed/constrained-random tests
• Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills
• Experience verifying at multiple levels of logic from SoCs to full system testing
• Experience with industry standard tools and scripting languages (Python) for automation
• Experience in SOC Architecture is a strong plus
• Experience with ARM/RISCV
• Experience with debugging system level issues
• Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc.
• Experience with formal verification techniques
• Excellent verbal and written communication skills