BT - Design Verification Sr Engineer

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General Summary:

Minimum Qualifications:

• 3 years to 6 years of strong experience in design verification
• Strong knowledge of HDLs like Verilog, System Verilog
• Proven experience of writing efficient constraint random tests
• Proven experience of building or maintaining a medium to complex SV/UVM environments
• Strong debugging and analytical skills and independent problem solving ability
• Proficient in debugging RTL/TB issues using Verdi or similar tools
• Demonstrate good judgment in selecting methods and techniques for obtaining solutions
• Strong communication skills, both written and verbal, with ability to evaluate and create test plans detailing complex features and relationships
• Bachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field

• Bachelor’s Degree in Engineering in Electronics, VLSI, Communications or related field
• 6 months of VLSI industry experience in verification

• Exposure to Bluetooth/BLE Technologies
• Knowledge on scripting languages such as Perl and(or) Python

• Functional Verification, Functional/Code Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC Integration, Formal checks

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