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Job Description
Job Title: Senior Verification Designer
Experience: 5+ Years
Location: Remote
Overview
Seeking experienced verification engineers to work on advanced AI connectivity and high-performance networking architectures.
Responsibilities:
Own verification strategy and execution for SoCs/IPs (Switches, NICs)
Build block and system-level verification environments
Develop UVM/SystemVerilog testbenches, checkers, and coverage
Drive coverage closure and signoff
Collaborate with RTL, architecture, and software teams
Contribute to verification methodology and infrastructure
Looking to get Placed? Try our Placement Guarantee Plan
5+ years in ASIC/FPGA verification (SystemVerilog, UVM)
Strong experience in networking architectures (Switches, NICs, SmartNICs)
Knowledge of Packet processing, RDMA, Ethernet, PCIe, MAC
Proven experience with high-performance systems
Formal, emulation, or FPGA experience is a plus
B.Tech/M.Tech/PhD in relevant field
Skills
High-performance SystemsIf an employer asks you to pay any kind of fee, please notify us immediately. Jobaaj does not charge any fee from the applicants and we do not allow other companies also to do so.
About Company
Important dates & deadlines?
Application Deadline
28 Jul 26, 06:16 PM IST
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