R&D Engineering, Sr Manager

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade building embedded memory IP that actually ships in production silicon, not just test chips that look good in papers. Managing teams through the full arc of SRAM, register file, and TCAM development has taught you that the hardest decisions happen early, at the architecture and bit cell level, and you have learned to guide engineers toward choices that hold up through tapeout and beyond.

You think in tradeoffs. Power versus area, speed versus yield, custom circuit elegance versus compiler automation constraints. When a layout is failing timing or a bit cell is not meeting yield targets at 3nm, you do not panic or wait for more data. You pull the team together, dig into the SPICE decks, and find the path forward.

Leading engineers across circuit design, physical implementation, and characterization means you speak multiple technical languages fluently. You can review a sense amplifier schematic in the morning, debug a Perl-based compiler flow after lunch, and walk a junior engineer through FinFET variation analysis before you leave. Your team trusts you because you have done the work and because you make them better at theirs.

At Synopsys, you will lead memory IP development that powers the most advanced semiconductor designs in the world.

What You'll Be Doing

• Lead a cross-functional team through the complete embedded memory development cycle, from bit cell analysis and architecture definition through circuit design, layout, verification, characterization, and model generation
• Drive SRAM, register file, TCAM, and ROM compiler development, balancing performance, power, area, and yield across advanced FinFET technology nodes
• Own schematic entry, transistor-level simulation, layout planning, and interface with CAD teams for full physical verification and timing model delivery
• Design and implement low-power, area-efficient memory circuits and architectures optimized for deep submicron and FinFET process variations
• Coordinate daily activities across your engineering team, prioritize workloads across multiple concurrent projects, and proactively address issues impacting schedule or quality
• Collaborate with internal teams and external customers to resolve technical challenges, align on solutions, and ensure memory IP meets functional and performance requirements
• Ramp quickly on existing flows, identify gaps or inefficiencies, and produce actionable work plans that drive projects to completion on aggressive timelines

The Impact You Will Have

• Your team will deliver production-ready memory compilers that enable customers to build complex SoCs at the most advanced process nodes
• Architectural and circuit decisions you guide will directly affect power, performance, and area outcomes in chips used across AI, mobile, automotive, and data center applications
• Memory IP you ship will be integrated into designs at scale, affecting yield, time-to-market, and product success for Synopsys customers globally
• Process improvements and automation you implement will increase team productivity and reduce development cycle time across future memory platforms
• Engineers you mentor will grow their skills in advanced circuit design, FinFET technology, and memory compiler automation, strengthening the team's long-term capability
• Technical solutions you drive will resolve cross-discipline challenges spanning circuit design, physical implementation, characterization, and modeling
• Your ability to deliver on schedule will enable downstream teams in verification, integration, and customer engagement to execute without delay

What You'll Need

• 10+ years of hands-on experience in embedded memory design, covering architecture, circuit design, physical implementation, compiler automation, characterization, and model generation
• BE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering
• Deep expertise in SRAM and register file architectures, including custom circuit techniques for sense amplifiers, write drivers, decoders, and bit cells
• Direct experience designing memory IP in advanced FinFET technology nodes, with strong understanding of variation-aware design, leakage management, and yield optimization
• Proficiency in scripting using Perl and Python for automation of design flows, characterization, and model generation
• Solid grounding in CMOS fundamentals, RC circuit analysis, digital design, and analog circuit basics, with practical application in memory design contexts
• Proven ability to lead engineering teams, manage multiple projects simultaneously, and deliver complex IP on schedule in a cross-site, multi-discipline environment

Who You Are

• You can walk into a design review, spot the issue in a timing path or a layout bottleneck, and guide the engineer toward a fix without taking over their work
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