Technical Lead II - VLSI

Department Icon IT / Software Development & Related
Posted: 6 days ago
8-15 years
Mountain View, India
IT / Software Development & Related
work from office
Full Time
Closes 6 Jan 2027

Posted: 6 days ago
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Job Description

Client Job Title: SOC Design Verification Engineer Who we are: At UST, we help the world s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact touching billions of lives in the process. Visit us at UST.com. The Opportunity: UST is looking for 02 SOC Design Verification Engineer. Key Roles & Responsibilities: We are seeking a highly motivated and experienced SoC Verification Engineer to join our team. As a key member of the verification team, you will be responsible for developing and executing verification plans for complex System-on-Chip (SoC) designs. You will work closely with design and architecture teams to ensure the quality and reliability of our products. Perform functional and performance verification of SoC designs using simulation, emulation, and formal verification techniques. Develop and execute comprehensive tests for functional verification and performance verification at the core and SOC level. Create and maintain verification environments using industry-standard tools and methodologies (e.g., UVM). Develop test benches, test cases, and coverage models using UVM, System Verilog, and C++. Debug and analyze simulation results to identify and resolve design issues. Collaborate with design and architecture teams to understand design specifications and identify potential verification challenges. Document verification results and track progress. Participate in code reviews and contribute to the improvement of verification methodologies. Desired Skills: Strong understanding of digital design principles and SoC architecture. Proficiency in hardware description languages (e.g., System Verilog, Verilog, VHDL). Proficiency in scripting languages (Python) and C/C++ Experience with verification methodologies (e.g., UVM, OVM, VMM). Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, ). Experience with debugging and analyzing simulation results. Strong problem-solving and analytical skills. Excellent communication and teamwork skills. Prior experience to industry standard protocols such as AXI, AHB, PCIe, DDR etc. will be an advantage Qualification: Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. 3-5 years of experience in SoC verification. Proficient in Python, C, C++ scripting language. Experience with soc level functional and performance verification. Familiarity with formal verification techniques is a plus. What we believe: We re proud to embrace the same values that have shaped UST since the beginning. Since day one, we ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone to champion diversity and inclusion and to place people at the centre of everything we do. Humility: We will listen, learn, be empathetic and help selflessly in our interactions with everyone. Humanity: Through business, we will better the lives of those less fortunate than ourselves. Integrity: We honour our commitments and act with responsibility in all our relationships. Equal Employment Opportunity Statement UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation. All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law. UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance. To support and promote the values of UST. Comply with all Company policies and procedures

Skills

PythonC++CSOCCommunicationTeamsVLSIVerilog

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